The present invention relates generally to frequency synthesizers, and more particularly to digitally controlled frequency synthesizers.
Most electronic communications devices include a frequency synthesizer. Conventional frequency synthesizers typically use an accurate reference oscillator, such as a crystal or surface acoustic wave (SAW) resonator, to control a controllable oscillator to generate one or more output signals at a desired frequency. The electronic device uses the output signal(s) to control timing and/or communication operations.
Direct digital synthesizers represent one type of frequency synthesizer. A direct digital synthesizer computes a digital sequence to address a table of values to produce samples of a waveform at a desired output frequency. The synthesizer produces an analog output signal at the desired frequency by performing a digital to analog conversion on the computed output sequence. While direct digital synthesizers may be manufactured on relatively small circuits, they often consume undesirably large amounts of power, especially when generating output signals at cellular communication frequencies.
A phase-locked loop (PLL) synthesizer represents another type of frequency synthesizer. PLL synthesizers use a frequency-controllable oscillator running at a frequency in the approximate desired frequency range to generate the output signal. To control the oscillator, the PLL divides the oscillator output signal in frequency by a predetermined factor n. The divided output is compared to a reference frequency using an analog phase detector to obtain a phase error signal indicative of the phase error in the output signal. The PLL incrementally adjusts the frequency of the oscillator based on the determined phase error to control the frequency of the output signal.
While PLL synthesizers can efficiently operate at high frequencies, such as cellular communication frequencies, the analog control components of the PLL synthesizer are difficult to manufacture on silicon chips primarily designed for digital logic circuits. This manufacturing difficulty increases as the silicon chip size decreases. In addition, the loop bandwidth of a conventional PLL is typically too narrow to suppress oscillator phase noise at frequencies far from the desired frequency. Thus, conventional PLL synthesizers typically require additional resonant circuits designed to suppress the undesirable oscillator phase noise. These resonant circuits cause additional manufacturing difficulties because they require a large chip area. Further, these resonant circuits may couple, causing undesirable interference effects.